1 ? fn9239.2 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2006-2007. all rights reserved all other trademarks mentioned are the property of their respective owners. isl97632 white led driver with digital dimming the isl97632 represents an efficient and highly integrated pwm boost led driver that is suitable for 1.8? to 3.5? lcds that employ 2 to 6 white leds for backlighting. with integrated schottky diode, ovp, and dynamic digital dimming capability, the isl97632 provides a simple, reliable, and flexible solution to the backlight designers. the isl97632 features a simple single-wire digital interface that provides a 5-bit dimming control. the dimming signal adjusts the fb voltage and ther efore the led brightness in a dc manner in 32 linear steps. an en pin can be used to provide a zero brightness setting or shutdown power saving function. the isl97632 is available in the 8 ld dfn (2mmx3mm) package. there are 14v, 18v, and 26v ovp options that are suitable for 3, 4, and 6 leds backlight applications respectively. the isl97632 is specified for operation over the -40c to +85c ambient te mperature at input voltage from 2.4v to 5.5v. pinout isl97632 (8 ld 2x3 tdfn) top view typical application circuit features ? 5-bit digital dimming control ? drives up to 6 leds in series ? ovp (14v, 18v and 26v for 3, 4, and 6 leds applications) ? integrated schottky diode ? 2.4v to 5.5v input ? 86% efficiency ? 1.4mhz switching frequency allows small lc ? enable for shutdown function or zero brightness setting ? 1a shutdown current ? internally compensated ? 8 ld dfn (2mmx3mm) ? pb-free plus anneal available (rohs compliant) applications ? led backlighting for - cell phones - smartphones -mp3 -pmp - automotive navigation panel - portable gps 2 3 4 1 7 6 5 8 gnd vin en sdin lx vout fbsw fb vin lx fbsw gnd vin en fb vout sdin 10h or 22h ordering information part number (note) part marking tape & reel (qty) package (pb-free) pkg. dwg.# isl97632irt14z-t elb 13? (6k pcs.) 8 ld 2x3 tdfn l8.2x3a isl97632irt14z-tk elb 13? (1k pcs.) 8 ld 2x3 tdfn l8.2x3a isl97632irt18z-t elc 13? (6k pcs.) 8 ld 2x3 tdfn l8.2x3a isl97632irt18z-tk elc 13? (1k pcs.) 8 ld 2x3 tdfn l8.2x3a isl97632irt26z-t eld 13? (6k pcs.) 8 ld 2x3 tdfn l8.2x3a isl97632irt26z-tk eld 13? (1k pcs.) 8 ld 2x3 tdfn l8.2x3a note: intersil pb-free plus anneal pr oducts employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-f ree peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. data sheet april 10, 2007
2 fn9239.2 april 10, 2007 absolute m aximum ratings (t a = +25c) thermal information input voltage ( v in ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6v lx voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 28v fbsw voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 28v all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6v operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c thermal resistance (typical, note 1) ja (c/w) jc (c/w) tdfn package (notes 1, 2). . . . . . . . . 70 10.5 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c lead temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . +300c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. important note: all parameters having min/max specifications are guaranteed over temper ature of -40c to +8 5c unless otherwise stated. typical values are for information purposes only at tj = tc = ta = +25c. note: 1. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 2. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications v in = v en = 3v parameter description condition min typ max unit v in supply voltage 2.4 5.5 v i in supply current en = 3v, enabled, not switching 0.8 1.5 ma en = 0v, disabled 1 a fsw switching frequency 1,300 1,450 1,600 khz dmax maximum duty cycle 90 95 % i lim lx current 400 470 ma r sw(lx) lx switch on-resistance ilx = 100ma 900 m ileak lx switch leakage current vlx = 28v 1 a vfb feedback voltage serial interface setting = 15 (center) 90 95 100 mv serial interface setting = s (s = 0,1..31) 9.8 + 5.68 x s mv serial interface setting = 0 9.8 mv ifb fb pin bias current vfb = 95mv 1 a r sw(fbsw) fbsw switch on-resistance 10 v diode schottky diode forward voltage idiode = 100ma, t a = +25c 600 850 mv ovp overvoltage protection isl97632irt14z 14 v isl97632irt18z 18 v isl97632irt26z 26 28 v vil logic low voltage 0.6 v vih logic high voltage 1.5 v t logic 1 timing range for logic 1 sdin = low 15 45 s t logic 0 timing range for logic 0 sdin = low 90 120 s t logic-load timing range for load sdin = low 215 s t logic-high minimum valid sdin high time sdin = high 3 s isl97632
3 fn9239.2 april 10, 2007 block diagram pin descriptions pwm logic controller gm amplifier 10 - 186mv pwm comparator vin en lx gnd fb rset c out l vin (2.4v to 5.5v) 2 to 6 leds cin isl97632 v out serial interface bandgap reference generator sdin fbsw en fet driver gm amp compensation current sense 1.4mhz oscillator and ramp generator pin number pin name description 1 gnd ground pin. connect to local ground. 2 vin input supply pin. connect to th e input supply voltage, the inductor and the input supply decoupling capacitor. 3 en enable pin. connect to enable signal to turn-on or off the device. active high. 4 sdin single-wire xsd digital interface. 5 fb feedback pin. connect to the cathode of bottom led and the sense resistor. 6 fbsw optional fb disconnect switch. 7 vout output pin. connect to the anode of the top led and the output filter capacitor. 8 lx switching pin. c onnect to inductor. isl97632
4 fn9239.2 april 10, 2007 single-wire serial interface the isl97632 uses a simple single-wire serial interface for programming the output bright ness of the leds. a 5-bit interface is used to give a to tal of 32 levels of output brightness. the interface uses a normally high connection for use with open-drain driving schemes and intersil?s proprietary xsd bus. when held low for between 15s and 45s, the interface registers a logic 1. when held low for between 90s and 120s the interface registers a logic 0. when held low for greater that 215s, the interface loads the last 5 bits into the brightne ss control register and updates the brightness level. the required minimum high time is 3s. this simple single-wire programming is summarized as follow: ? logic 0 = negative pulse >90s and <120s ? logic 1 = negative pulse >15s and <45s ? load = negative pulse >215s figure 1 shows an example of pr ogramming a binary code of 10100 and load it in to the device serial register. the serial interface is automatically reset to 0 when the device is disabled, or enters uv lo. therefore, when the part is enabled, the output brightness is automatically set to the minimum level. 30s 100s 220s '1' '0' '1' '0' '0' 'load' 0 200 400 600 800 1000 1200 s figure 1. single-wire xsd interface isl97632
5 fn9239.2 april 10, 2007 typical performace curves figure 2. efficiency vs led current figure 3. quiescent current vs v in (enab = hi) figure 4. load regulation (v in = 4v) figure 5. line regulation figure 6. iled vs programming codes 50 55 60 65 70 75 80 85 90 0 5 10 15 20 25 30 35 40 45 i out (ma) efficiency (%) 4.2v in 4 leds out (22h) 3.6v in 4 leds out (15h) 3.6v in 4 leds out (10h) 4.2v in 4 leds out (10h) 3.6v in 4 leds out (22h) 4.2v in 4 leds out (15h) - 0.2 0 0.2 0.4 0.6 0.8 1 0 v in (v) iq (ma) 1234 5 19.92 19.96 20.00 20.04 20.08 0 5 10 15 20 25 30 v out (v) i o (ma) 19.62 19.64 19.66 19.68 19.70 19.72 19.74 19.76 2.53.03.54.04.55.05.5 v in (v) i o (ma) 0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 code = decimal i o (ma) r set = 4.7 isl97632
6 fn9239.2 april 10, 2007 detailed description the isl97632 uses a constant frequency, current mode control scheme to provide excellent line and load regulation. there are three ovp models for driving 3, 4, and 6 leds and their ovp thresholds are set at 14v, 18v, and 26v respectively. the isl97632 operates from an input voltage of 2.4v to 5.5v and ambient temper ature from -40c to +85c. the switching frequency is around 1.45mhz and allows the driver circuit to employ sm all lc components. the forward current of the led is set using the r set resistor. in the steady state mode, the led current is given by equation 1: where s is the 5-bit serial interface setting or digital code from 0 to 31 programmed in the xsd single-wire interface. the default setting is 0 and the vfb is at minimum. dimming control the isl97632 powers up to provide minimium current. by programming the digital code with the intersil?s xsd single- wire interface as shown in figure 1, the current can be changed linearly with the digital code from 0 to 31. figure 6 shows led current versus the programming codes. overvoltage protection the isl97632 comes with overvoltage protection. the ovp trip points are at 14v, 18v, and 26v for isl97632irt14z, isl97632irt18z, and isl97632irt26z respectively. the maximum numbers of leds and ovp threshold are shown in table 1. when the device reaches the ovp, the lx stops switching, disabling the boost circuit until v out falls about 7% below the ovp threshold. at this point, lx will be allowed to switch again. the ovp event will not cause the device to shutdown there are three ovp options so that the 3 leds application should use the 14v ovp device and the 6 leds application should use the 26v ovp device. an output capacitor that is only rated fo r the required voltage range can therefore be used which will optimize the component costs in some cases. shut-down an active high en pin is normally on but this pin can be used as a shutdown power saving function or zero brightness setting. when taken low the en pin places the isl97632 into power down mode down where the supply current is reduced to less than 1a. the en pin cannot be used as pwm input as the part resets to 0 whenever en is low. to resume previous setting, the device needs to be reprogrammed. output disconnect the isl97632 features a fbsw feedback disconnect switch that can be used in between the led and rset for an optional short-circuit protecti on. for example, the user may build an external short circuit detection to monitor the v out . if the v out goes low due to one or more leds which are shorted, the circuit can release the en and fbsw switch to disconnect the leds. components selection the input capacitance is typically 0.22f to 4.7f. the output capacitor should be in the range of 0.22f to 1f. x5r or x7r type of ceramic capacitors of the appropriate voltage rating are recommended. when choosing an inductor, make sure the average and peak current ratings are adequate by using the following equations (80% efficiency assumed): where: ? i l is the peak-to-peak inductor current ripple in amps ? l is the inductance in h. ?f osc is the switching freq uency, typically 1.45mhz the isl97632 supports a wide range of inductance values (10h~82h). for lower inductor values or lighter loads, the boost inductor current may become discontinuous. for high boost inductor values, the boost inductor current will be in continuous mode. in addition to the inductor value and switching frequency, the input voltage, the number of leds and the led current also affect whether the converter operates in continuous conduction or discontinuous cond uction mode. both operating modes are allowed and normal. the discontinuos conduction mode yields lower efficiency due to higher peak current. compensation the product of the output ca pacitor and the load create a pole while the inductor creates a right half plane zero. both attributes degrade the phase margin but the isl97632 has an internal compensation network that ensures the device operates reliabily under the specified conditions. the internal compensation and the highly integrated functions of the isl97632 make it a design friendly device to be used in high volume high reliability applications. table 1. part no. ovp max no. of leds max iled isl97632irt14z 14v 3 70ma isl97632irt18z 18v 4 50ma isl97632irt26z 26v 6 30ma i led s () v fb s () r set -------------------- 9.8mv 5.68mv s + r set -------------------------------------------------------- == (eq. 1) i lavg i led v out ? 0.8 v in ? --------------------------------- = (eq. 2) i lpk i lavg 1 2 -- - i l ? + = (eq. 3) i l v in v out v in ? () ? lv out f osc ?? -------------------------------------------------- - = (eq. 4) isl97632
7 fn9239.2 april 10, 2007 applications efficiency improvement figure 2 shows the efficiency measurements. the choice of the inductor has a significant im pact on the power efficiency. as shown in equation 4, the higher the inductance, the lower the peak current therefore the lower the conduction and switching losses. on the other hand, it has also a higher series resistance. nevertheless, the efficiency improvement from lowering the peak current is greater than the impact of the resistance increase with larger value of inductor. efficiency can also be improv ed for systems that have high supply voltages. since the isl97632 can only supply from 2.4v to 5.5v, v in must be seperated from the high supply voltage for the boost circuit as shown in figure 7 and the efficiency improvement is shown in figure 8. 8 leds operation for medium size lcds that need more than 6 low power leds for backlighting, such as a portable media player or automotive navigation panel displays, the voltage range of the isl97632 is not sufficient. however, the isl97632 can be used as an led controller with an external protection mosfet connected in cascode fashion to achieve higher output voltage. a conceptual 8 leds driver circuit is shown in figure 9. a 60v logic level n-channel mosfet is configured such that its drai n ties between the inductor and the anode of schottky diode, its gate ties to the input, and its source ties to the isl97632 lx node connecting to the drain of the internal switch. when th e internal switch turns on, it pulls the source of m1 down to ground, and lx conducts as normal. when the internal switch turns off, the source of m1 will be pulled up by the follower action of m1, limiting the maximum voltage on the isl97632 lx pin to below vin, but allowing the output voltage to go much higher than the breakdown limit on the lx pin. the switch current limit and maximum duty cycle will not be c hanged by this setup, so input voltage will need to be carefully considered to make sure that the required output voltage and current levels are achievable. because the source of m1 is effectively floating when the internal lx switch is off, the drain-to-source capacitance of m1 may be sufficient to capacitively pull the node high enough to breaks down the gate oxide of m1. to prevent this, vout should be connected to vin, allowing the internal schottky to limit the peak voltage. this will also hold the vout pin at a known low voltage, preventing the built in ovp function from causing problems. this ovp function is effectively useless in this mode as the real output voltage is outside its intended range. if the user wants to implement their own ovp protection (to pr event damage to the output capacitor, they should insert a zener from vout to the fb pin. in this setup, it would be wise not to use the fbsw to fb switch as otherwise the zene r will have to be a high power one capable of dissipating the entire led load power. then the led stack can then be conne cted directly to the sense resistor and via a 10k resistor to fb. a zener can be placed from vout to the fb pin allowing an over voltage event to pull up on fb with a low breakdown current (and thus low power zener) as a result of the 10k resistor. sepic operation for applications where the output voltage is not always above the input voltage, a buck or boost regulation is needed. a sepic (single ended primary inductance vs = 12v l1 22 1 2 r1 4 c3 0.22 d2 d3 d1 d5 d6 d4 isl97632 fbsw lx vout sdin vin fb gnd c1 1 25ma c2 0.1 en v in = 2.7v to 5.5v figure 7. seperate high input voltage for higher efficiency operation 5101520 90 85 70 0 75 80 25 30 iled (ma) efficiency (%) v in = 4v 6 leds l1 = 22h r1 = 4 v s = 12v v s = 9v figure 8. efficiency improvement with 9v and 12v inputs vout lx isl97632 sdin vin fbsw gnd fb en r1 6.3 d3 d4 d5 d6 d7 d8 l1 2.2 12 v in = 2.7v to 5.5v c3 4.7 d0 10bq100 m1 fqt13n06l d1 c1 1 sk011c226kar c2 0.1 d2 figure 9. conceptual 8 leds high voltage driver isl97632
8 fn9239.2 april 10, 2007 converter) topology, (shown in figure ), can be considered for such an application. a single cell li-ion battery operating a cellphone backlight or flashlight is one example. the battery voltage is between 2.5v and 4.2v depending on the state of charge. on the other hand, the output may require only one 3v to 4v medium power led for illumination because the lig ht guard of the backlight assembly is optimized or it is a cost efficiency trade off reason. in fact, a sepic configured led driver is flexible enough to allow the output to be well above or below the input voltage, unlike the previous example. another example is when the number of leds and input requirements are different from platform to platform, a common circuit and pcb that fit all the platforms, in some cases, may be beneficial enough that it outweights the disadvantage of adding additional component cost. l1 and l2 can be a coupled inductor in one package. the simplest way to understand sepic topology is to think about it as a boost regulator in which the input voltge is level shifted downward at the same magnitude and the lowest reference level starts at -v in rather than 0v. the sepic works as follows; assu me the circuit in figure 10 operates normally when the isl97632 internal switch opens and it is in the pwm off state after a short duration where few lc time constants elapsed, the circuit is considered in the steady-state within the pwm off period that l1 and l2 are shorted. v b is therefore shorted to the ground and c3 is charged to v in with v a = v in . when the isl97632 internal switch closes and the circuit is in the pwm on state, v a is now pulled to ground. since the voltage in c3 cannot be changed instantenously, v b is shifted downward and becomes -v in . the next cycle when the isl97632 switch opens, v b boosts up to the target ted output like the standard boost regulator operation, except the lowest reference point is at -v in . the output is approximated as: where d is the on-time of the pwm duty cycle. the convenience of sepic come s with some trade off in addition to the additional l and c costs. the efficiency is usually lowered because of the relatively large efficiency loss through the schottky diode if the output voltage is low. the l2 series resistance also contributes additional loss. figure 11 shows the efficiency measurement of a single led application as the input va ries between 2.7v and 4.2v. note, v b is considered the level-shifted lx node of a standard boost regulator. the higher the input voltage, the lower the v b voltage will be during pwm on period. the result is that the efficiency will be lower at higher input voltages because the sepic has to work harder to boost up to the required level. this behavior is the opposite to the standard boost regulator?s and the comparison is shown in figure 11. pcb layout considerations the layout is very important for the converter to function properly. r set must be located as close as possible to the fb and gnd pins. longer traces to the leds are acceptable. similarly, the supply decoupling cap and the output filter cap should be as close as possible to the vin and vout pins. the heat of the ic is mainly dissipated through the thermal pad of the package. maximize the copper area connected to this pad if possible. in addition, a solid ground plane is always helpful for the emi performance. c1 1 l1 22 1 2 v a v b vin = 2.7v to 5.5v 22 l2 c3 1 c4 0.22 d1 r1 1 c2 0.1 vin en sdin lx vout fbsw fb gnd figure 10. sepic led driver v out v in d 1d ? () ------------------ = (eq. 5) v in = 2.7v v in = 4.2v 1 led l1 = l2 = 22h c3 = 1f r1 = 4.7 0 5 10 15 20 iled (ma) efficiency (%) 76 72 68 64 60 figure 11. efficiency meas urement of a single led sepic driver isl97632
9 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn9239.2 april 10, 2007 isl97632 thin dual flat no-lead plastic package (tdfn) // nx (b) section "c-c" 5 (a1) bottom view a 6 area index c c 0.10 0.08 side view 0.15 2x e a b c 0.15 d top view cb 2x 6 8 area index nx l e2 e2/2 ref. e n (nd-1)xe (datum a) (datum b) 5 0.10 8 7 d2 b a m c n-1 12 plane seating c a a3 nx b d2/2 nx k for even terminal/side terminal tip c l e l c c l8.2x3a 8 lead thin dual flat no-lead plastic package symbol millimeters notes min nominal max a 0.70 0.75 0.80 - a1 - - 0.05 - a3 0.20 ref - b 0.20 0.25 0.32 5,8 d 2.00 bsc - d2 1.50 1.65 1.75 7,8 e 3.00 bsc - e2 1.65 1.80 1.90 7,8 e 0.50 bsc - k0.20 - - - l 0.30 0.40 0.50 8 n 8 2 nd 4 3 rev. 0 6/04 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd refers to the number of terminals on d. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.25mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are prov ided to assist with pcb land pattern design efforts, see intersil technical brief tb389.
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